In recent years, the demand for small-size nonvolatile semiconductor memories with large capacity is increasing rapidly, and especially, compared with the conventional NOR type EEPROM, NAND type EEPROM which can expect high integration has attracted attention.
As for NAND type EEPROM, one line of one source/drain line formed in the diffusion zone of the silicon active region is formed to one bit line BL. That is, one NAND type memory cell unit is constituted to one bit line BL. Here, if a design rule is set to F (Feature Size), the line/space of bit line BL is set to 1F/1F, and the line/space of word line WL is also set to 1F/1F. For this reason, the cell size of one memory cell transistor MTr is set to 2F×2F=4F2. Since two selective gate transistors are provided in one NAND type memory cell unit, if the size of these selective gate transistors is considered as an overhead α, substantial one cell size becomes 4F2+α.
On the other hand, the following patent documents 1 discloses the nonvolatile semiconductor memory device which a trench is formed in a semiconductor substrate in order to minimize one cell size and the NAND memory cell unit forms lengthwise at the wall part of the trench side.                Patent documents 1: Japanese Laid-Open Patent Publication No. H7-45797        
The technology disclosed in this patent document is that as shown FIG. 57, a trench region TC is formed in a semiconductor substrate, and memory cell transistor MTr is formed on the sidewall of the both sides of this trench region TC, respectively. In this case, a floating gate FG is formed along with the side wall of inner side of the trench region, and a source/drain SD is formed as a diffusion zone along with side wall of trench region of a semiconductor substrate. That is, as for this NAND type memory cell unit, a plurality of memory cell transistors MTr are formed along with the sidewall of trench region TC, and for this reason, a source/drain current flows along with the sidewall of a trench region. A bit line BL is formed for every NAND type memory cell unit via an interlayer insulating film. The line/space in this bit line BL is 1F/1F.
However, in the technology disclosed in the above-mentioned patent documents 1, only one silicon activation region can be located in the bit line pitch of 2F, and memory cell size cannot be effectually reduced by half, and the further high integration is demanded.
Then, the present invention is conducted in view of the above subject, and it aims at making NAND type EEPROM in three dimensions and locating source/drain line in the bit line pitch of 2F in two silicon activation regions. That is, it purposes that two NAND type memory cell units are located to one bit line. And thereby it purposes to reduce a memory cell size by half, offering the nonvolatile semiconductor memory device which can realize low bit cost as a result.